The present invention is directed to a tuning module. More particularly, the present invention is directed to a tuning module that operates a dual frequency phase-locked loop synthesized tuner.
A dual frequency phase-locked loop ("PLL") synthesized tuner is a well-known device that is used to convert high-frequency signals to low-frequency signals. Dual frequency PLL synthesized tuners typically include an upconverter and a downconverter, and are implemented in, for example, cable television receivers and satellite communication receivers.
Typical dual frequency PLL synthesized tuners operate by setting local oscillators, which are generated by PLLs, to the frequencies required by the upconverter and the downconverter. However, the carrier-to-noise ratio ("CNR") of the output of these tuners is frequently degraded due to a variety of problems. One problem is frequency offset, which can be caused by external and internal variations in component tolerances and calibration. Another problem is internal and external interference. Internal interference can be caused by internal sources such as mixing products from local oscillators, digital switching noise, and harmonics from clocks. External interference can be caused by external sources such as radiated or conducted sources of radio frequency ("RF").
Degraded carrier-to-noise ratio can be avoided by performing a different type of adjustment to the tuner for each type of problem. However, known dual frequency PLL synthesized tuners do not permit individual adjustments of each PLL; most known tuners adjust only a single PLL, and this adjustment is based on only the frequency of a desired channel. Therefore known dual frequency PLL synthesized tuners do not adequately compensate for frequency offset and interference problems that degrade the carrier-to-noise ratio.
Based on the foregoing, there is a need for a tuning module that operates a dual frequency PLL synthesized tuner to optimize the carrier-to-noise ratio of the output.